? semiconductor components industries, llc, 2014 august, 2014 ? rev. 11 1 publication order number: mc74hc540a/d mc74hc540a octal 3-state inverting buffer/line driver/line receiver high?performance silicon?gate cmos the mc74hc540a is identical in pinout to the ls540. the device inputs are compatible with standard cmos outputs. external pull?up resistors make them compatible with lsttl outputs. the hc540a is an octal inverting buffer/line driver/line receiver designed to be used with 3?state memory address drivers, clock drivers, and other bus?oriented systems. this device features inputs and outputs on opposite sides of the package and two anded active?low output enables. the hc540a is similar in function to the hc541a, which has noninverting outputs. features ? output drive capability: 15 lsttl loads ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 2.0 to 6.0 v ? low input current: 1 a ? high noise immunity characteristic of cmos devices ? in compliance with the jedec standard no. 7 a requirements ? chip complexity: 124 fets or 31 equivalent gates ? nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable ? these devices are pb?free and are rohs compliant figure 1. logic diagram 18 y1 2 a1 17 y2 3 a2 16 y3 4 a3 15 y4 5 a4 14 y5 6 a5 13 y6 7 a6 12 y7 8 a7 11 y8 9 a8 oe1 oe2 1 19 output enables data inputs inverting outputs pin 20 = v cc pin 10 = gnd http://onsemi.com 1 20 marking diagrams soic?20 dw suffix case 751d 74hc540a awlyywwg hc 540a alyw tssop?20 dt suffix case 948e 20 1 see detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ordering information a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g or = pb?free package (note: microdot may be in either location) soic?20 tssop?20 19 20 18 17 16 15 14 2 1 34567 v cc 13 8 12 9 11 10 oe2 y1 y2 y3 y4 y5 y6 y7 y8 oe1 a1 a2 a3 a4 a5 a6 a7 a8 gnd pin assignment 20?lead (top view) l l h x l l x h l h x x function table inputs output y oe1 oe2 a h l z z z = high impedance x = don?t care
mc74hc540a http://onsemi.com 2 maximum ratings symbol parameter value unit v cc dc supply voltage ?0.5 to +7.0 v v i dc input voltage ?0.5 to v cc + 0.5 v v o dc output voltage (note 1) ?0.5 v o v cc + 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 35 ma i o dc output sink current 35 ma i cc dc supply current per supply pin 75 ma i gnd dc ground current per ground pin 75 ma t stg storage temperature range ?65 to +150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias +150 c ja thermal resistance soic tssop 96 128 c/w p d power dissipation in still air at 85 c soic tssop 500 450 mw msl moisture sensitivity level 1 f r flammability rating oxygen index: 30% ? 35% ul 94 v0 @ 0.125 in v esd esd withstand voltage human body model (note 2) machine model (note 3) charged device model (note 4) > 2000 > 200 > 1000 v i latchup latchup performance above v cc and below gnd at 85 c (note 5) 300 ma stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. i o absolute maximum rating must be observed. 2. tested to eia/jesd22?a114?a. 3. tested to eia/jesd22?a115?a. 4. tested to jesd22?c101?a. 5. tested to eia/jesd78. recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types ?55 +125 c t r , t f input rise and fall time (figure 3) v cc = 2.0 v v cc = 4.5 v v cc = 6.0 v 0 0 0 1000 500 400 ns functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. 6. unused inputs may not be left open. all inputs must be tied to a high? or low?logic input voltage level.
mc74hc540a http://onsemi.com 3 dc characteristics (voltages referenced to gnd) v cc v guaranteed limit symbol parameter condition ?55 to 25 c 85 c 125 c unit v ih minimum high?level input voltage v out = 0.1 v |i out | 20 a 2.0 3.0 4.5 6.0 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 v v il maximum low?level input voltage v out = v cc ? 0.1 v |i out | 20 a 2.0 3.0 4.5 6.0 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 v v oh minimum high?level output voltage v in = v il |i out | 20 a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in = v il |i out | 3.6 ma |i out | 6.0 ma |i out | 7.8 ma 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 v ol maximum low?level output voltage v in = v ih |i out | 20 a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v ih |i out | 3.6 ma |i out | 6.0 ma |i out | 7.8 ma 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 i in maximum input leakage current v in = v cc or gnd 6.0 0.1 1.0 1.0 a i oz maximum three?state leakage current output in high impedance state v in = v il or v ih v out = v cc or gnd 6.0 0.5 5.0 10.0 a i cc maximum quiescent supply current (per package) v in = v cc or gnd i out = 0 a 6.0 4 40 160 a ac characteristics (c l = 50 pf, input t r = t f = 6 ns) v cc v guaranteed limit symbol parameter ?55 to 25 c 85 c 125 c unit t plh , t phl maximum propagation delay, input a to output y (figures 2 and 4) 2.0 3.0 4.5 6.0 80 30 18 15 100 40 23 20 120 55 28 25 ns t plz , t phz maximum propagation delay, output enable to output y (figures 3 and 5) 2.0 3.0 4.5 6.0 110 45 25 21 140 60 31 26 165 75 38 31 ns t pzl , t pzh maximum propagation delay, output enable to output y (figures 3 and 5) 2.0 3.0 4.5 6.0 110 45 25 21 140 60 31 26 165 75 38 31 ns t tlh , t thl maximum output transition time, any output (figures 2 and 4) 2.0 3.0 4.5 6.0 60 22 12 10 75 28 15 13 90 34 18 15 ns c in maximum input capacitance 10 10 10 pf c out maximum 3?state output capacitance (output in high impedance state) 15 15 15 pf c pd power dissipation capacitance (per buffer) (note 7) typical @ 25 c, v cc = 5.0 v, v ee = 0 v pf 35 7. used to determine the no?load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc .
mc74hc540a http://onsemi.com 4 figure 2. switching waveform v cc gnd input a output y t phl oe1 or oe2 50% v cc gnd output y t pzl output y t pzh high impedance v ol v oh high impedance 10% 90% t plz t phz 50% 50% t plh 90% 50% 10% t r t thl t f t tlh figure 3. switching waveform 90% 50% 10% 50% c l * *includes all probe and jig capacitance test point device under test output figure 4. test circuit figure 5. test circuit c l * *includes all probe and jig capacitance test point device under test output 1k connect to v cc when testing t plz and t pzl . connect to gnd when testing t phz and t pzh . figure 6. logic detail one of eight inverters input a oe1 oe2 output y v cc to 7 other inverters
mc74hc540a http://onsemi.com 5 pin descriptions inputs a1, a2, a3, a4, a5, a6, a7, a8 (pins 2, 3, 4, 5, 6, 7, 8, 9) data input pins. data on these pins appear in inverted form on the corresponding y outputs, when the outputs are enabled. controls oe1, oe2 (pins 1, 19) output enables (active?low). when a low voltage is applied to both of these pins, the outputs are enabled and the device functions as an inverter. when a high voltage is applied to either input, the outputs assume the high impedance state. outputs y1, y2, y3, y4, y5, y6, y7, y8 (pins 18, 17, 16, 15, 14, 13, 12, 11) device outputs. depending upon the state of the output enable pins, these outputs are either inverting outputs or high?impedance outputs. ordering information device package shipping ? mc74hc540adwg soic?20 wide (pb?free) 38 units / rail MC74HC540ADWR2G soic?20 wide (pb?free) 1000 tape & reel mc74hc540adtr2g tssop?20 (pb?free) 2500 tape & reel nlv74hc540adtr2g* tssop?20 (pb?free) 2500 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable
mc74hc540a http://onsemi.com 6 package dimensions tssop?20 dt suffix case 948e?02 issue c dim a min max min max inches 6.60 0.260 millimeters b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. 110 11 20 pin 1 ident a b ?t? 0.100 (0.004) c d g h section n?n k k1 jj1 n n m f ?w? seating plane ?v? ?u? s u m 0.10 (0.004) v s t 20x ref k l l/2 2x s u 0.15 (0.006) t detail e 0.25 (0.010) detail e 6.40 0.252 --- --- s u 0.15 (0.006) t 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc74hc540a http://onsemi.com 7 package dimensions soic?20 dw suffix case 751d?05 issue g 20 1 11 10 b 20x h 10x c l 18x a1 a seating plane h x 45 e d m 0.25 m b m 0.25 s a s b t e t b a dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 12.65 12.95 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of b dimension at maximum material condition. on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemni fy and hold scillc and its officers, em ployees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 mc74hc540a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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